The present invention relates to the field of computer processor architecture. In particular the present invention discloses a method and apparatus for improving memory operation efficiency by dividing memory write operations into a prefetch stage and store stage.
Computer processor designers continually attempt to improve the performance of computer processors. To improve processor performance, many novel processor design approaches have been created such as pipeline execution, register renaming, out-of-order instruction execution, and branch prediction with speculative execution of instructions fetched after a predicted branch. However, the speed of computer memories has not increased proportionally with the speed increases of computer processors. To alleviate any speed bottleneck that may be caused by the relatively slow main memory, most processors use a local high-speed cache memory.
The speed of computer processors now often stretches the limitations of high-speed cache memories. In order to most efficiently utilize a local high-speed cache memory system, a processor must be carefully integrated the cache memory system using read buffers and write buffers. The read buffers and write buffers provide a conduit between processor execution units and the memory subsystems. If the design of the read buffers, write buffers, and the associated control logic is optimized then the computer processor will not be slowed down by the memory system. It would therefore be desirable to have an improved memory interface within a computer processor.
A method of performing memory write operations in a computer processor is disclosed. The method issues a pre-fetch operation that loads a needed cache line into a cache memory. Then, a subsequent store operation is issued. The subsequent store operation stores a data value into the cache line that was pre-fetched into the cache memory.
Other objects, features, and advantages of present invention will be apparent from the accompanying drawings and from the following detailed description that follows below.